The most prestigious law school admissions discussion board in the world.
|
 |
 
|
TSMC can't do backside power delivery but Intel can. That's where we're at
| Gregory Bovino | 01/27/26 |
| Gregory Bovino | 01/27/26 |
Poast new message in this thread
Date: January 27th, 2026 12:17 PM Author: Gregory Bovino EUV whatever, the engineering required to pull this off is insane and probably compensates for Intel's struggles with EUV (http://www.autoadmit.com/thread.php?thread_id=5827337&forum_id=2]#49623403) |
Date: January 27th, 2026 12:22 PM Author: Gregory Bovino The clever separation of the power delivery network from data delivery is especially beneficial to high-performance computing (HPC) devices. Here, backside power addresses the increasing problem of parasitic voltage (IR) drop, which drastically reduces product performance and gets worse with each process node. By delivering power using slightly fatter, less resistive lines on the backside, rather than inefficient frontside approaches, backside power delivery networks (BPDNs) reduces power losses by up to 30% due to less voltage droop. The silicon frontside interconnects are freed up for routing signal interconnects only, and can even lower cost due to fewer expensive EUV lithography steps.
https://semiengineering.com/backside-power-delivery-nears-production/ |